The uncomfortable truth behind the hype around 2D semiconductor performance

Researchers at Duke University have uncovered a significant flaw in the common laboratory testing method used to evaluate ultrathin 2D semiconductors, materials considered promising candidates to replace silicon in future computer chips. The widely used back-gated transistor design, favored for its ease of fabrication and rapid experimentation, artificially inflates transistor performance by up to six times compared to realistic operating conditions. This inflation arises from a phenomenon called contact gating, where the gate electric field affects not only the semiconductor channel but also the material beneath the metal contacts, reducing electrical resistance and making the device appear faster and more efficient than it truly is. To address this, the researchers constructed a symmetric dual-gate transistor allowing direct comparison between configurations with and without contact gating while keeping the physical structure constant. Their findings showed that contact gating roughly doubles performance in larger devices and amplifies to about a fivefold increase in scaled-down devices relevant for commercial chip technologies. This effect also significantly reduces transfer length, highlighting contact gating as a critical but previously under