US engineers develop 3D chip that offers order-of-magnitude speed gains

US engineers from Stanford, Carnegie Mellon, University of Pennsylvania, and MIT, in collaboration with SkyWater Technology, have developed a novel 3D multilayer computer chip architecture that significantly outperforms traditional 2D chips. Unlike flat chips where components are spread out on a single surface, this new design stacks ultra-thin layers vertically, connected by dense vertical wiring that enables rapid data movement akin to elevators in a high-rise building. Early hardware tests show the prototype achieves roughly four times the performance of comparable 2D chips, while simulations of taller versions with more layers predict up to a twelve-fold improvement on AI workloads, including those based on Meta’s LLaMA model. This breakthrough addresses the longstanding "memory wall" bottleneck, where data transfer speeds limit processing despite faster computing elements and limited nearby memory. By vertically integrating memory and computation, the chip drastically shortens data pathways, improving both throughput and energy efficiency. The team claims this architecture could realistically lead to 100- to 1